Electrostatic discharge (ESD) is a known problem in the manufacturing and the using of integrated circuits. Typically, transistors have thin oxides and insulating layers that can be damaged by the electrostatic discharge, and special care is required to protect the integrated circuits from the damage caused by the ESD.
In high-voltage (HV) applications such as applications using light-emitting devices (LED) and liquid crystal display (LCD) devices, ESD protection circuits are also needed. The ESD protection circuits may include ESD power clamps coupled between HV power nodes and electrical grounds. Conventional ESD power clamps may be implemented using RC-HVMOS transistors or cascaded bipolar-junction transistors (BJT), which are electrically broken down by ESD transients to conduct ESD currents. However, the conventional ESD power clamps suffer from drawbacks. For example, the RC-HVMOS devices require large chip areas. The BJTs in the power clamps have non-flexible design window, and the trigger voltage for the ESD protection is limited by the number of cascaded BJTs.